View AD1871YRS-REEL_2566269.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad1871 rev. 0 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 stereo audio, 24-bit, 96 khz, multibit - adc functional block diagram data p ort mclk reset clatch/( m /s) cclk/( 256 /512) cin/(df1) fi lter e ngine ad1871 lrclk bclk dout din cout/(df0) casc xctrl mu ltibit - m odulator a nalog input bu ffer de cimator mu ltibit - m odulator a nalog input bu ffer de cimator spi p ort cl ock div ider vinlp vinln vref vinrp vinrn capln caplp avdd dvdd odvdd caprn caprp agnd dgnd features 5.0 v stereo audio adc with 3.3 v tolerant digital interface supports 96 khz sample rates supports 16-/20-/24-bit word lengths multibit sigma-delta modulators with ?erfect differential linearity restoration?for reduced idle tones and noise floor 105 db (typ) dynamic range supports 256/512 and 768 f s master clocks flexible serial data port allows right-justified, left-justified, i 2 s compatible and dsp serial port modes cascadable (up to four devices) from a single dsp sport device control via spi compatible serial port or optional control pins on-chip reference 28-lead ssop package applications professional audio mixing consoles musical instruments digital audio recorders, including cd-r, md, dvd-r, dat, hdd home theater systems automotive audio systems multimedia product overview the ad1871 is a stereo audio adc intended for digital audio applications requiring high performance analog-to-digital conversion. it features two 24-bit conversion channels each with programmable gain amplifier (pga), multibit sigma-delta modulator, and decimation filters. each channel provides 105 db of dynamic range, making the ad1871 suitable for applications such as digital audio recorders and m ixing consoles. each of the ad1871? input channels (left and right) can be configured as either differential or single-ended (two inputs muxed with internal single-ended-to-differential conversion). the input pga features a gain range of 0 db to 12 db in steps of 3 db. the - ? modulator features a proprietary multibit architecture that realizes optimum performance over an audio bandwidth with standard audio sampling rates of 32 khz up to 96 khz. the decimation filter response features very low pass- band ripple and excellent stop-band attenuation. the ad1871? audio data interface supports all common interface f ormats such as i 2 s, left-justified, right-justified as well as other modes that allow for convenient connection to general-purpose digital signal processors (dsps). the ad1871 also features an spi compatible serial control port that allows for convenient control of device parameters and functionality such as sample word-width, pga settings, interface modes, and so on. the ad1871 operates from a single 5 v power supply?ith an optional digital interfacing capability of 3.3 v. it is housed in a 28-lead ssop package and is characterized for operation over the temperature range ?0 c to +105 c.
ad1871 ? rev. 0 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 test conditions unless otherwise specified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 analog performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 low-pass digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 high-pass digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 master clock (mclk) and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 data interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 digital i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 filter responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 device performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 digital decimating filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 high-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 adc coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 analog input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 control register i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 control register ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 control register iii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 peak reading registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 external control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 master /slave select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mclk mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 serial data format select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 modulator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 analog interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
rev. 0 ? ad1871?pecifications test conditions unless otherwise noted supply voltages . . . . . . . . . . . . . . . . . . . . . . 5.0 v ambient temperature . . . . . . . . . . . . . . . . . 25 c input clock (f clkin ) [256 f s ] . . . . . . . . . . 12.288 mhz input signal . . . . . . . . . . . . . . . . . . . . . . . . . 991.768 hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.5 db full scale (dbfs) (differential, pga/mux enabled) measurement bandwidth . . . . . . . . . . . . . . . 23.2 hz to 19.998 khz word width . . . . . . . . . . . . . . . . . . . . . . . . . 24 bits load capacitance on digital outputs . . . . . 100 pf input voltage high (v ih ) . . . . . . . . . . . . . . . 2.4 v input voltage low (v il ) . . . . . . . . . . . . . . . 0.8 v master mode, data i 2 s justified analog performance parameter min typ max unit conditions resolution 24 bits differential input pga/mux enabled dynamic range (20 hz to 20 khz, ?0 db input) unweighted 98 103 db a-weighted 100 105 db signal-to-noise ratio 106 db total harmonic distortion + noise ?5 db input = ?.5 dbfs (thd+n) ?03 db input = ?0 dbfs multibit modulator only modulator output @ 5.6448 mhz dynamic range (a-weighted) 102 db single-ended input pga/mux enabled dynamic range (20 hz to 20 khz, ?0 db input) unweighted 103 db a-weighted 105 db signal-to-noise ratio 106 db total harmonic distortion + noise ?5 db input = ?.5 dbfs (thd+n) ?03 db input = ?0 dbfs differential input (bypass) pga/mux disabled dynamic range (20 hz to 20 khz, ?0 db input) unweighted 103 db a-weighted 106 db signal-to-noise ratio 106 db total harmonic distortion + noise ?6 db input = ?.5 dbfs (thd+n) ?04 db input = ?0 dbfs differential input (f s = 96 khz) pga/mux enabled; amc = 1 dynamic range (20 hz to 20 khz, ?0 db input) unweighted 103 db a-weighted 106 db signal-to-noise ratio 106 db total harmonic distortion + noise ?7 db input = ?.5 dbfs (thd+n) ?04 db input = ?0 dbfs analog inputs differential input range ( full scale) ?.828 +2.828 v input impedance (pga/mux) 8 k w differential input impedance (bypass) 40 k w differential input impedance (pga/mux) 4 k w single ended v ref 2.138 2.25 2.363 v dc accuracy gain error ?0 % interchannel gain mismatch ?.2 ?.01 +0.2 db gain drift 100 ppm/ c crosstalk (eiaj method) ?00 db
rev. 0 ? ad1871?pecifications low-pass digital filter characteristics (f s = 48 khz) parameter min typ max unit decimation factor 128 pass-band frequency 21.77 khz stop-band frequency 26.23 khz pass-band ripple 0.01 db stop-band attenuation 120 db group delay 910 m s low-pass digital filter characteristics (f s = 96 khz) parameter min typ max unit decimation factor 64 pass-band frequency 43.54 khz stop-band frequency 52.46 khz pass-band ripple 0.01 db stop-band attenuation 120 db group delay 460 m s high-pass digital filter characteristics (f s = 48 khz) parameter min typ max unit cutoff frequency 2 hz high-pass digital filter characteristics (f s = 96 khz) parameter min typ max unit cutoff frequency 4 hz master clock (mclk) and reset timing mnemonic description min typ max unit comment t mch mclk high width 20 ns t mcl mclk low width 20 ns t pdr reset low pulsewidth 20 ns mclk t mch t mcl t pdr r eset figure 1. mclk/ reset timing
rev. 0 ? ad1871 data interface timing (standalone mode?aster) mnemonic description min typ max unit comment t bdly bclk delay 20 ns from mclk rising t bldly lrclk delay to low 10 ns from bclk falling t bddly dout delay 10 ns from bclk falling t bddly bclk lrclk dout le ft-justified mode dout righ t-justified mode lsb dout i 2 s-justified mode t bdly t bldly msb msb? msb msb 8-bit clocks (24-bit data) 12-bit clocks (20-bit data) 16-bit clocks (16-bit data) mclk 1 figure 2. master data interface timing
ad1871 ? rev. 0 data interface timing (standalone mode?lave) mnemonic description min typ max unit comment t bch bclk high width 30 ns t bcl bclk low width 30 ns t bdsd dout delay 20 ns from bclk falling t lrs lrclk setup 10 ns to bclk rising t lrh lrclk hold 5 ns from bclk rising t bdsd bcl k lrclk dout l eft-justified mo de dout ri ght-justified mo de lsb dout i 2 s-justified mo de t bch t dbp t bcl msb msb?1 msb msb 8-bit clocks (24-bit data) 12-bit clocks (20-bit data) 16-bit clocks (16-bit data) t lrs figure 3. slave data interface timing
rev. 0 ? ad1871 data interface timing (cascade mode?aster) mnemonic description min typ max unit comment t bchdc bclk high delay 20 ns from mclk rising t bcldc bclk low delay 20 ns from mclk falling t blrdc lrclk delay 10 ns from bclk rising t bddc dout delay 10 ns from bclk rising t bdis din setup 10 ns to bclk rising t bdih din hold 10 ns from bclk rising lrclk mclk dout bclk t bchdc t bcldc t blrdc t bddc figure 4. master cascade interface timing data interface timing (cascade mode?lave) mnemonic description min typ max unit comment t bchc bclk high width 30 ns t bclc bclk low width 30 ns t bdsdc dout delay 20 ns from bclk rising t lrsc lrclk setup 10 ns to bclk rising t lrhc lrclk hold 5 ns from bclk rising t bdis din setup 10 ns to bclk rising t bdih din hold 10 ns from bclk rising lrclk dout bclk t lrsc t bdsdc t bchc t bclc t lrhc figure 5. slave cascade interface timing data interface timing (modulator mode) mnemonic description min typ max unit comment t moch modclk high width mclk ns t mocl modclk low width mclk ns t mhdd mod data high delay 30 ns from mclk rising t mldd mod data low delay 20 ns from mclk falling t mmdr modclk delay rising 30 ns mclk falling to modclk rising t mmdf modclk delay falling 20 ns mclk falling to modclk falling d[0? 3] mo dclk t mhdd t moch t mocl t mldd figure 6. modulator mode timing
ad1871 ? rev. 0 control interface (spi) timing mnemonic description min typ max unit comment t cch cclk high width 40 ns t ccl cclk low width 40 ns t ccp cclk period 80 ns t cds cdata setup time 10 ns to cclk rising t cdh cdata hold time 10 ns from cclk rising t cls clatch setup time 10 ns to cclk rising t clh clatch hold time 10 ns from cclk rising t coe cout enable 15 ns from clatch falling t cod cout delay 20 ns from cclk falling t cots cout three-state 25 ns from clatch rising t cch t ccl cclk clatch cin cout d15 d14 d12 d11 d10 d07 d06 d04 d03 d02 d01 d00 d13 d09 d08 d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 d05 t chd t csu t ccl t clh figure 7. control interface timing digital i/o parameter min typ max unit input voltage high (v ih ) 2.4 v input voltage low (v il ) 0.8 v input leakage (i ih @ v ih = 5 v) 10 m a input leakage (i il @ v il = 0 v) 10 m a output voltage high (v oh @ i oh = ? ma) odvdd ?0.4 v v output voltage low (v ol @ i ol = +2 ma) 0.4 v input capacitance 15 pf power parameter min typ max unit supplies voltage, avdd, and dvdd 4.5 5 5.5 v voltage, odvdd 2.7 5.5 v analog current 40 45 ma analog current?ower-down (mclk running) 4.0 6.0 m a digital current, dvdd 18 22 ma digital current, odvdd 0.5 1.0 ma digital current?ower-down (mclk running) dvdd * 0.8 2.0 ma digital current?ower-down (mclk running) odvdd * 1.0 15.0 m a power supply rejection 1 khz 300 mv p-p signal at analog supply pins ?6 db 20 khz 300 mv p-p signal at analog supply pins ?7 db * reset held low. temperature range parameter min typ max unit specifications guaranteed 25 c functionality guaranteed ?0 +105 c storage ?5 +150 c specifications subject to change without notice.
rev. 0 ad1871 ? absolute maximum ratings min typ max unit dvdd to dgnd and odvdd to dgnd 0 6 v avdd to agnd 0 6 v digital inputs dgnd ?0.3 dvdd + 0.3 v analog inputs agnd ?0.3 avdd + 0.3 v agnd to dgnd ?.3 +0.3 v reference voltage indefinite short circuit to ground soldering (10 sec) 300 c ordering guide package package model temperature description option ad1871yrs ?0 c to +105 c ssop rs-28 AD1871YRS-REEL ?0 c to +105 c ssop rs-28 in 13 reel (1500 pieces) eval-ad1871eb evaluation board caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1871 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad1871 vref caplp capln vinlp vinln avdd xctrl mclk cclk/( 256 /512) cout/(df0) cin/(df1) dgnd dvdd clatch/( m /s) agnd caprp caprn vinrp vinrn agnd casc lrclk bclk dout din dgnd odvdd reset
ad1871 ?0 rev. 0 pin function descriptions pin input/ no. output mnemonic description 1i mclk master clock. the master clock input determines the sample rate of the device. mclk can be 256, 512, or 768 times the sampling frequency. 2i cclk 1 control port bit clock?lock signal for control port (spi) interface. this pin is recon- figured in the external control mode (pin xctrl is high), see below. 3 i/o cout 1, 2 control port data out?erial data output from the control port (spi) interface (in read- back). this pin is reconfigured in the external control mode (pin xctrl is high), see below; or in modulator mode (bit mme of control register ii is set), see below. 4i cin 1 control port data input?erial data input for control port (spi) interface. this pin is reconfigured in the external control mode (pin xctrl is high), see below. 5i clatch 1 control port frame sync?rame sync (framing signal) for control port (spi) interface. this pin is reconfigured in the external control mode (pin xctrl is high), see below. 6i dvdd 5 v digital core supply 7i dgnd digital ground 8i xctrl external control enable. this pin is used to select the control mode for the device. when xctrl is low, control is via the spi compatible control port (pins cclk, clatch, cin, and cout). when xctrl is enabled (high), control of several device functions is possible by hardware pin strapping (pins 256 /512, m /s, df1, and df0). in external control mode, all other functions are in default state (please refer to the control register descriptions and external control section). 9i avdd 5 v analog supply 10 i vinln left channel, negative input (via mux/pga) 11 i vinlp left channel, positive input (via mux/pga) 12 i/o capln left external filter capacitor (negative input to modulator) 13 i/o caplp left external filter capacitor (positive input to modulator) 14 o vref reference voltage output. it is recommended to connect a capacitor combination of 10 m f in parallel with 0.1 m f between vref and agnd (pin 15). (see layout recommendations.) 15 i agnd analog ground 16 i/o caprp right external filter capacitor (positive input to modulator) 17 i/o caprn right external filter capacitor (negative input to modulator) 18 i vinrp right channel, positive input (via mux/pga) 19 i vinrn right channel, negative input (via mux/pga) 20 i agnd analog ground 21 i casc cascade enable. this pin enables cascading of up to four ad1871 devices to a single dsp serial port (see cascading section). 22 i dgnd digital ground 23 i odvdd digital interface supply. the digital interface can operate from 3.3 v to 5.0 v (nominal). 24 i reset reset 25 i/o din 2 serial data input. serial data input pin, only valid when the device is configured in cas- cade mode (pin casc is high). this pin is reconfigured in modulator mode (bit mme of control register ii is set), see below. 26 o dout 2 audio serial data output. this pin is reconfigured in modulator mode (bit mme of control register ii is set), see below. 27 i/o bclk 2 audio serial bit clock. the bit clock is the audio data serial clock and determines the rate of audio data transfer. this pin is reconfigured in modulator mode (bit mme of control register ii is set), see below. 28 i/o lrclk 2 left/right clock. this clock, also known as the word clock, determines the sampling rate. it is an output or input depending on the status of master /slave. this pin is reconfigured in modulator mode (bit mme of control register ii is set), see below. notes 1 external control mode (see pg 11) 2 modulator mode (see pg 11)
rev. 0 ad1871 ?1 pin function redefinition in external control mode pin input/ no. output mnemonic description 2i 256 /512 clock rate select. this pin is used to select between an mclk of 256 f s (pin low) or 512 f s (pin high). 3i df0 data format select 0. this pin is used as the low bit (df0) of the data format selection (see section on external control). 4i df1 data format select 1. this pin is used as the high bit (df1) of the data format selection (see section on external control). 5i m /s master/slave select. this pin is used to select between the master (pin low) or slave (pin high) modes. pin function redefinition in modulator mode pin input/ no. output mnemonic description 3o modclk this pin provides a clock output that allows the user to decode the left and right channel modulator outputs. it is similar to a left/right clock but runs (nominally) at 5.6448 mhz and gates a 4-bit modulator output word in each phase (see section on modulator mode). 25 o d3 bit 3 of the modulator output word 26 o d2 bit 2 of the modulator output word 27 o d1 bit 1 of the modulator output word 28 o d0 bit 0 of the modulator output word
ad1871 ?2 rev. 0 terminology dynamic range the ratio of a full-scale input signal to the integrated input noise in the pass band (20 hz to 20 khz), expressed in decibels (db). dynamic range is measured with a ?0 db input signal and is equal to (s/[thd+n]) + 60 db. note that spurious harmonics are below the noise with a ?0 db input, so the noise level establishes the dynamic range. the dynamic range is specified with and without an a-weight filter applied. signal to (total harmonic distortion + noise) (s/[thd+n]) the ratio of the root-mean-square (rms) value of the fundamen- tal input signal to the rms sum of all other spectral components in the pass band, expressed in decibels (db). pass band the region of the frequency spectrum unaffected by the attenu- ation of the digital decimator? filter. pass-band ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. stop band the region of the frequency spectrum attenuated by the digital decimator? filter to the degree specified by stop-band attenuation. gain error with a near full-scale input, the ratio of the actual output to the expected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of the outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per c. crosstalk (eiaj method) ratio of response on one channel with a grounded input to a full-scale 1 khz sine-wave input on the other channel, expressed in decibels. power supply rejection with no analog input, signal present at the output when a 300 mv p-p signal is applied to power supply pins, expressed in decibels of full scale. group delay intuitively, the time interval required for an input pulse to appear at the converter? output, expressed in milliseconds (ms). more precisely, the derivative of radian phase with respect to radian frequency at a given frequency. glossary adc?nalog-to-digital converter dsp?igital signal processor imclk?nternal master clock signal, used to clock the deci- mating filter section. (its frequency must be 256 f s. ) mclk?xternal master clock signal applied to the ad1871. its frequency can be 256, 512, or 768 f s . mclk is divided internally to give an imclk frequency that must be 256 f s . modclk?his is the - modulator clock that determines the sample rate of the modulator. ideally, it should not exceed the lower of 6.144 mhz or 128 f s . the modclk is derived from the imclk by a divider that can be selected as /2 or /4. mux?ultiplexer pga?rogrammable gain amplifier
rev. 0 ?3 rev. 0 t ypical performance characteristicsad1871 filter responses frequency ? normalized to f s 0 ?20 ?160 015 5 magnitude ? db 10 ?80 ?100 ?120 ?140 ?40 ?60 tpc 1. sinc filter response (amc = 0) frequency ? normalized to f s 0 ?20 ?160 015 5 magnitude ? db 10 ?80 ?100 ?120 ?140 ?40 ?60 tpc 2. first half-band filter response frequency ? normalized to f s 0 ?20 ?160 015 5 magnitude ? db 10 ?80 ?100 ?120 ?140 ?40 ?60 tpc 3. comb compensation filter response frequency ? normalized to f s 0 ?20 ?160 015 5 magnitude ? db 10 ?80 ?100 ?120 ?140 ?40 ?60 tpc 4. second half-band filter response frequency ? normalized to f s 0 0 magnitude ? db ?50 ?100 ?150 51015 tpc 5. composite filter response (amc = 0) frequency ? normalized to f s 0 0 magnitude ? db ?50 ?100 ?150 0.5 1.0 1.5 2.0 tpc 6. composite filter response (pass band section) (amc = 0)
ad1871 ?4 rev. 0 device performance curves frequency ? hz 5 0 0 ?5 ?10 ?15 ?20 ?25 ?30 5101520 magnitude ? db tpc 7. high-pass filter response, f s = 48 khz frequency ? hz 5 0 magnitude ? db 0 ?5 ?10 ?15 ?20 ?25 ?30 5101520 tpc 8. high-pass filter response, f s = 96 khz khz 0 ?60 ?120 ?20 ?40 ?80 ?100 ?140 ?160 ?180 20 2 dbfs 4681012 14 16 18 tpc 9. 1 khz tone at ?.5 dbfs, (32 k-point fft), f s = 48 khz khz 0 ?60 ?120 ?20 ?40 ?80 ?100 ?140 ?160 ?180 20 2 dbfs 46810 12 14 16 18 tpc 10. 1 khz tone at ?0 dbfs, (32 k-point fft), f s = 48 khz khz 0 ?60 ?120 ?20 ?40 ?80 ?100 ?140 ?160 ?180 20 2 dbfs 46810121 41618 tpc 11. 1 khz tone at ?0 dbfs, (32 k-point fft), f s = 48 khz dbr ?40 ?70 ?20 ?30 ?50 ?60 ?80 ?90 ?100 ?15 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?10 ?5 db tpc 12. thd+n vs. input amplitude at 1 khz, f s = 48 khz
rev. 0 ad1871 ?5 khz ?70 ?60 ?80 ?90 ?100 ?110 20 2 dbfs 46810121 41618 tpc 13. thd+n vs. input frequency at ?.5 dbfs, f s = 48 khz khz ?90 ?105 ?120 20 2 db 46810 12 14 16 18 ?95 ?100 ?110 ?115 tpc 14. channel separation vs. frequency at ?.5 dbfs, f s = 48 khz frequency?mhz 00.20.40 .6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.1 db ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 tpc 15. fft of modulator output at ?.5 dbfs, f s = 6.144 mhz
ad1871 ?6 rev. 0 functional description clocking scheme the mclk pin is the input for the master clock frequency to the device. nominally the mclk frequency will be 256 f s for correct operation of the device. however, if the user? mclk is a multiple of 256 f s (perhaps 512 f s or 768 f s ), it is pos sible to divide down the mclk frequency to a suitable internal master clock frequency (imclk) using the mclk divider block as shown in figure 8. the divide options can be chosen from pass- through (/1), /2, or /3 corresponding with 256 f s , 512 f s , or 768 f s mclks, respectively. the mclk divider can be con- trolled using the mcd1?cd0 bits of control register iii. (see table xiii.) the resulting internal mclk (imclk) is used to run the decimating and filtering engine and must be chosen to be at a ratio of 256 f s . sinc fi lter half -band filt ers imclk /2 /4 12.288mhz/ 24.576mhz 6.144mhz 384khz/ 768khz 48khz/ 96khz amc bit (cont reg i) 0/ 1 6.144mhz a nalog i nput /1 /2 /3 mclk mclk divi der imclk divi der 48khz/ 96khz hpe bit (cont reg i) modclk - mo dulator high-pass filt ers figure 8. clocking scheme to modulator and filter engine modulator the ad1871? analog - modulator section comprises a second order multibit implementation using analog device? proprietary technology for best performance. as shown in figure 9, the two analog integrator blocks are followed by a flash adc section that generates the multibit samples. the output of the flash adc, which is thermometer encoded, is decoded to binary for output to the filter sections and is scrambled for feedback to the two integrator stages. the modulator is optimized for operation at a sampling rate of 6.144 mhz (which is 128 f s at 48 khz sampling and 64 f s at 96 khz sampling). the modulator clock control (amc bit in control register i) is used to select the modulator clock (modclk) as a ratio from the imclk. the modulator clock divider options are /2 (default) for 48 khz operation and /4 for 96 khz operation. when operating with an imclk of 12.288 mhz, the default divider setting (/2) gives a modulator clock of 6.144 mhz. when operating with an imclk of 24.576 mhz, the alternate divider setting (/4) gives a modulator clock of 6.144 mhz (see figure 8). if it is required to operate the device at a different output sample rate than those detailed above, perhaps 44.1 khz or 88.2 khz, the decimation filter cutoff characteristics can then be determined from the normalized frequency response plot shown in tpc 6. flash adc scrambler thermo- meter to binary decoder feedback dacs from analog input section digital output (4 bits/6.144mhz) figure 9. modulator block diagram
rev. 0 ad1871 ?7 digital decimating filters the filtering and decimation of the ad1871? modulator data stream is implemented in an embedded dsp engine. the first stage of filtering is the sinc filtering, which has selectable deci- mation (selected by the modulator clock control bit (amc, see modulator section). the default decimation in the sinc stage provides a sample rate reduction of 16; this corresponds with a modclk rate of 128 f s . the alternate setting of the amc bit gives a sinc decimation factor of 8 that corresponds with a modclk rate of 64 f s . the output of the sinc decimator stage is at a rate of 8 f s . the filter engine implements two half-band fir filter sections and a sinc compensation stage that together give a further decimation factor of 8. please refer to tpcs 1 through 4 for details on the responses of the sinc and fir filter sections. tpc 5 gives the composite response of the sinc and fir filters. high-pass filter the ad1871 features an optional high-pass filter section that provides the ability of rejecting dc from the output data stream. the high-pass filter is enabled by setting bit 8 (hpe) of control register i to 1. please refer to tpc 7 and tpc 8 for details of the high-pass filter characteristics. adc coding the adc? output data stream is in a two? complement en coded format. the word width can be selected from 16 bits, 20 bits, or 24 bits (see table vi and table vii). the coding scheme is detailed in table i. table i. adc coding code level 011111.......1111 +full scale 000000........0000 0 (ref level) 100000........0001 ?ull scale analog input section the analog input section comprises a differential pga stage. it can also be configured for single-ended inputs, allowing two such inputs to be selected via a multiplex switch. the pga has five gain settings (see table v) ranging from 0 db to 12 db in 3 db steps. in differential mode, the vinxp and vinxn input pins are connected to a pair of inverting amplifiers whose outputs are connected to the capxn and capxp pins, respectively. (see figure 10.) capxn capxp v cm vinxp vinxn v cm figure 10. differential analog input in single-ended mode, either vinxp or vinxn can be selected as the input. the pair of input inverting amplifiers is reconfig- ured as a single-ended-to-differential conversion stage. again the outputs of the differential section are connected to pins capxp and capxn (see figure 11). capxn capxp v cm vinxp vinxn v cm figure 11. single-ended analog input the analog input section is enabled (powered on) by default on reset. if it is required to bypass the analog input section by using the modulator input pins (capxp and capxn) directly, then the analog input section must be powered down by setting bits mer and mel in control register iii. serial data interface the ad1871? serial data interface consists of three pins (lrclk, bclk, and sdata). lrclk is the framing sig- nal for left and right channel samples and its frequency is equal to the sampling frequency (f s ). bclk is the serial clock used to clock the data samples from the ad1871 and its fre- quency is equal to 64 f s (giving 32 bclk periods for each of the left and right channels). sdata outputs the left and right channel sample data coincident with the falling edge of bclk. the serial data interface supports all the popular audio interface standards, such as i 2 s, left-justified (lj), and right-justified (rj), as well as the serial interfaces of modern dsps. the interface mode is selected by programming the bits df1?f0 of control register ii (see tables vi and viii). the data sample width can be selected from 16, 20, or 24 bits by programming bits ww1?w0 of control register ii (see tables vi and vii).
ad1871 ?8 rev. 0 i 2 s mode in i 2 s mode, the data is left-justified, msb first, with the msb placed in the second bclk period following the transition of the lrclk. a high-to-low transition of the lrclk signifies the beginning of the left channel data transfer, while a low-to- high transition on the lrclk signifies the beginning of the right channel data transfer (see figure 12). left channel right channel msb?2 msb?1 lsb+2 lsb+1 lsb msb?2 msb?1 msb lsb+2 lsb+1 lsb msb lrclk bclk dout msb figure 12. i 2 s mode lj mode in lj mode, the data is left-justified, msb first, with the msb placed in the first bclk period following the transition of the lrclk. a high-to-low transition of the lrclk signifies the be ginning of the right channel data transfer, while a low-to-high transition on the lrclk signifies the beginning of the left channel data transfer (see figure 13). msb?2 msb?1 lsb+2 lsb+1 lsb msb?2 msb?1 msb lsb+2 lsb+1 lsb msb?1 msb lrclk bclk dout left channel right channel msb figure 13. left-justified mode rj mode in rj mode, the data is right-justified, lsb last, with the lsb placed in the last bclk period preceding the transition of the lrclk. a high-to-low transition of the lrclk signifies the beginning of the right channel data transfer, while a low-to- high transition on the lrclk signifies the beginning of the left channel data transfer (see figure 14). dout lsb msb?2 msb?1 lsb+2 lsb+1 ms b ? 2 ms b ? 1 msb ls b + 2 lsb+1 lsb bclk lrclk left channel right channel msb lsb figure 14. right-justified mode dsp mode in dsp mode, the lrclk signal becomes a frame sync signal that pulses high for the bclk period prior to the msb (or in the bclk period of the previous lsb?2 bits). the data is left- justified, msb first, with the msb placed in the bclk period following the lrclk pulse (see figure 15). in i 2 s and lj modes, since the data is left-justified, differences in data word-width between the ad1871 and the controller are not catastrophic since the msbs are guaranteed to be transferred. there may, however, be a slight reduction in performance depending on the scale of the mismatch. in rj mode, however, differences in word-width between the ad1871 and controller have a catastrophic effect on signal performance as the msbs of each sample may be lost due to the mismatch. dout msb?1 lsb+2 lsb+1 lsb msb?1 lsb+2 lsb+1 lsb msb msb?1 msb lrclk left channel right channel bclk msb figure 15. dsp mode
rev. 0 ad1871 ?9 cascade mode the ad1871 supports cascading of up to four devices in a daisy-chain configuration to the serial port of a dsp. in cascade mode, each device loads an internal 64-bit shift register with the results of the left and right channel conversions. the 64- bit r egister is split into two subframes of 32 bits each; the first for left channel data and the second for right channel data. the results are left-justified, msb first within the subframes, and the word-width setting in control register ii applies. remaining bits within the subframe, beyond the conversion word-width, are set to zero. please refer to figure 16. up to four devices can be connected in a daisy chain as shown in figure 17. all devices must be set in cascade mode by tying the casc pin of each device to a logic high. the first device in the chain (device 4) has its din pin tied to logic low. its dout pin is connected to the din pin of device 3 w hose dout is in turn connected to the din pin of device 2. this daisy chaining is continued until the dout of device 1 is connected to the dsp? serial port rx data line (dr0). the dsp? rx serial clock (rxclk0) is connected to the bclk pin of all ad1871 devices and the dsp? rx frame sync (rfs0) is connected to the lrclk pin of all ad1871 devices. 64-bit frame 32-bit left subframe 32-bit right subframe 16-bit result 16-bit result 20-bit result 24-bit result 20-bit result 24-bit result figure 16. dsp mode the dsp can be the master and supply the frame sync and serial clock to the ad1871s, or one of the ad1871s can be set as the master with the dsp and all other ad1871s set to slave. each sampling period begins with a frame sync being gener- ated ei ther by the dsp or one of the ad1871s, depending on the master /slave selection. the frame-sync pulse causes each device to load the 64-bit data i/o register with the left and right adc results. t hese results are then clocked toward the dsp where they are received in the following order: device 1, left; device 1, right; device 2, left; device 2, right; device 3, left; device 3, right; device 4, left; and device 4, right. the dsp? serial port must be programmed to accept 32-bit word lengths regardless of the ad1871 word length. the number of sample words to be accepted per sample interval will be determined by the number of ad1871 devices in cascade, up to a maximum of eight words corresponding with the maximum number of four devices. figure 17 also shows the connection of a sepa rate dsp serial port interface to the control port (spi) interface of the cascaded ad1871s. again this cascade is implemented as a daisy chain, where the control words for the four devices are output in sequence (depending on the hookup ?1, 2, 3, and 4 in the example) to be latched simultaneously at each device by the common clatch. in this mode, it is necessary to send a control word for each device (16 bits the number of devices) from the spi port of the control host. the clatch signal can be controlled from a separate programmable output line. it is also possible to have individual read/write of the ad1871s using separate clatch controls for each device. when using cascade mode, the data interface defaults to left- justified, msb first data, regardless of the state of the interface mode selection (by spi or external control). the timing relationships of the cascade mode are shown in figure 18. ad1871 no.1 clatch cclk cout cin lrclk bclk dout din ad1871 no.2 clatch cclk cout cin lrclk bclk dout din ad1871 no.3 clatch cclk cout cin lrclk bclk dout din ad1871 no.4 clatch cclk cout cin lrclk bclk dout din dt1 dr1 txclk1/rxclk1 tfs1/rfs1 rfs0 rxclk0 dr0 adsp-21xxx sharc dsp figure 17. dsp mode
ad1871 ?0 rev. 0 the spi compatible control port features four signals (cclk, clatch, cdata, and cout). the clatch signal is an enable line that must be low to allow communication to or from the control port. the cclk is the serial clock that clocks in serial data via the cdata pin and clocks out serial data via the cout pin. figures 20 and 21 show details of the control port timing. table ii. register address map address control register 0000 control register i 0001 control register ii 0010 control register iii 0011 peak reading register i 0100 peak reading register ii dout lrclk de vice 1 device 2 device 3 device 4 bclk dout left channel bclk msb msb ?1 msb ?2 lsb +1 lsb 123 23 24 right channel 123 2324 msb msb ?1 msb ?2 lsb +1 lsb figure 18. cascade mode data interface timing cin clatch de vice 1 device 2 device 3 device 4 cclk cin cclk msb msb ?1 lsb +1 lsb figure 19. cascade mode control port timing control/status registers the ad1871? operating mode is set by programming three, 10-bit control registers via an spi compatible port. table iii details the format of the ad1871 control words, which are 16 bits wide with a 4-bit address field in positions 15 through 12, a read/ write bit in p osition 11, a reserved bit in position 10, and 10 bits of regis ter data (corre sponding to the control regis- ter width) in positions 9 through 0. the three control words occupy addresses 0000b through 0010b in the register map (see table ii). the ad1871 also features two readback (status) registers that can be enabled to track the peak reading on each of the chan- nels (left and right). these 6-bit results are read back via the spi compatible port in a 16-bit frame similar to that of the control words.
rev. 0 ad1871 ?1 table iii. control/status word format 15-12 11 10 9 6 5 4 3210 address r/ w reserved control/status data bits (9?) cclk clatch cin cout d15 d14 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d13 figure 20. writing to register using control port d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 cclk clatch cin cout d15 d14 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d13 figure 21. reading from register using control port table iv. control register i (address 0000b, write only) 15?2 11 10 9 8 7 6 5 4 3 2 1 0 0000 0 0 pre hpe pd amc agl2 agl1 agl0 agr2 agr1 agr0 9 pre peak reading enable (0 = disabled (default); 1 = enabled) 8 hpe high-pass filter enable (0 = disabled (default); 1 = enabled) 7p d power-down control (1 = power-down; 0 = normal operation (default)) 6 amc adc modulator clock (1 = 64 f s ; 0 = 128 f s (default)) 5? agl2?gl0 input gain (left channel, see table v) 2? agr2?gl0 input gain (right channel, see table v) control register i control register i contains bit settings for control of analog front end gain, modulator clock selection, power-down control, high-pass filtering, and peak hold. analog gain control the ad1871 features an optional analog front end with select- able gain. gain is selected using three control bits for each channel, giving five separate and independent gain settings on each chan nel. bits 2 through 0 (agr2?gr0) set the analog gain for the right channel, while bits 5 through 3 (agl2?gl0) set the analog gain for the left channel. table v shows the analog gain corre- sponding to the bit settings in ag x2?dx0. table v. analog gain settings agx2 agx1 agx0 gain (db) 00 0 0 (default) 001 3 010 6 011 9 100 12 101 0 110 0 111 0
ad1871 ?2 rev. 0 table vi. control register ii (address 0001b) 15?2 11 10 9 876 5 43210 0001 0 0 mme df1 df0 ww1 ww0 m /s mur mul 9? reserved 7 mme modulator mode enable (0 = normal mode (default), 1 = mod mode) 6? df1?f0 data format (see table viii) 4? ww1?w0 word width (see table vii) 2 m /s master /slave select (0 = master mode (default); 1 = slave mode) 1 mur mute control, right channel (0 = disabled (default); 1 = enabled) 0 mul mute control, left channel (0 = disabled (default); 1 = enabled) table vii. word-width settings ww1 ww0 word width (no. of bits) 00 24 (default) 0120 1016 11 reserved data format the ad1871? serial data interface can be configured from a choice of popular interface formats, including i 2 s, left-justified, right-justified, or dsp modes. bits df1?f0 are programmed to select the interface format (mode) as shown in table viii. table viii. data interface format settings * df1 df0 interface mode 00i 2 s (default) 01 right-justified 10 dsp 11 left-justified * please refer to the serial data interface section in the functional description for more details on the various interface modes. modulator mode enable the ad1871 defaults to the conversion of the analog audio to linear, pcm-encoded digital outputs. modulator mode allows the user to bypass the digital decimation filter section and access the multibit sigma-delta modulator outputs directly. when in this mode, certain pins are redefined (see modulator mode) and the modulator output (at a nominal rate of 128 f s ) is avail able on the modulator data pins (d[0?]). to enable the modu- lator mode, set the mme bit to high. modulator clock the modulator clock can be chosen to be either 128 f s or 64 f s . the amc bit (bit 6) is used to select the modulator? clock rate. when amc is set to 0 (default), the modulator clock is 128 f s . otherwise, if set to 1, the modulator clock is 64 f s . this bit is normally set depending on whether the desired sampling frequency is 48 khz or 96 khz and is also influenced by the selected mclk frequency. please refer to the functional description section for more information on mclk selection and sampling rates. power-down power-down of the active clock signals within the ad1871 is effected by writing a logic 1 to bit 7 (pd). in power-down mode, digital activity is suspended and analog sections are powered down, with the exception of the reference. high-pass filter the ad1871? digital filtering engine allows the insertion of a high-pass filter (hpf) to effectively block dc signals from the output digital waveform. setting bit 8 (hpe) enables the high-pass filter. for more details of the hpf, refer to the functional description section. peak reading enable the ad1871 has two readback registers that can be enabled to store the peak readings of the left and right channel adc results. to enable the peak readings to be captured, the peak r eading enable bit (pre), bit 9, must be set to logic 1. when set to logic 0, the peak reading capture is disabled. control register ii control register ii contains bit settings for control of left/right channel muting, data sample word width, data interface format, and direct modulator bitstream output. mute control the left and right data channels can be muted to digital zero by setting the mul and mur bits (bits 0 and 1), respectively. if a channel is muted, its output data stream will remain at digital zero, regardless of the amplitude of the input signal. setting the bit to 1 mutes the channel while setting the bit to 0 restores normal operation. master /slave select the ad1871 can operate as either a slave device or a master device. in slave mode, the controller must provide the lrclk and bclk to determine the sample rate and serial bit rate. in master mode, the ad1871 provides the lrclk and bclk as outputs that are applied to the controller. the ad1871 defaults to master mode ( m /s is low ) on reset. word width the ad1871 allows the output sample word width to be selected from 16, 20, and 24 bits wide. compact disc (cd) com patibility may require 16 bits, while many modern digital audio formats require 24-bit sample resolution. bits ww1?w0 are programmed to select the word width. table vii details the control register bit settings corresponding to the various word width selections.
rev. 0 ad1871 ?3 single-ended mode enable the single-ended mode enable bits (sel and ser for left and right channels, respectively), when set to 1, are used to configure single-ended input on vinxp and vinxn (input is selected by state of mxl and mxr). in this mode, single-ended inputs taken from either vinxp or vinxn (selected using the mux select bits?xl and mxr) are internally converted to a differential format to be applied to the modulator section (see table xii). table xii. differential/single-ended select sel ser input setting 0x left channel input ? differential 1x left channel input ? single-ended x0 right channel input ? differential x1 right channel input ? single-ended master clock divider the master clock divider allows the division of the external mclk frequency to a more suitable internal master clock frequency (imclk). imclk must be 256 f s ; therefore, if the available mclk is not at 256 f s but is a multiple of this, the mcd allows conversion of mclk to a suitable i mclk at 256 f s (see table xiii). table xiii. master clock divider settings mcd1 mcd0 mclk division 00 imclk = mclk (/1) 01 imclk = mclk/2 10 imclk = mclk/3 11 imclk = mclk (/1) table ix. control register iii (address 0010b) 15?2 11 10 9 8 7 6 5 4 3 2 1 0 0010 0 0 mcd1 mcd0 sel ser mel mxl mer mxr 9? reserved (should be programmed to 0) 7? mcd1?cd0 master clock divider (see table xiii) 5 sel single-ended enable, left channel (0 = differential (default) ; 1 = single-ended) 4 ser single-ended enable, right channel (0 = differential (default) ; 1 = single-ended) 3 mel mux/pga disable, left channel (0 = enabled (default) ; 1 = disabled) 2 mxl mux select, left channel (0 = vinlp selected (default) ; 1 = vinln selected) 1 mer mux/pga disable, right channel (0 = enabled (default) ; 1 = disabled) 0 mxr mux select, right channel (0 = vinrp selected (default) ; 1 = vinrn selected) control register iii control register iii contains bit settings for configuration of the analog input section (both left and right channels). mux enable the mux enable left (mel) and mux enable right (mer) are used to enable the analog buffers. when these bits are set to 1, the analog input buffers are powered down and input signals must be applied directly to the modulator inputs via the capxp and capxn pins. (see figure 23). when mel and mer are set to 0 (default condition after reset), the analog input section is enabled, (see table x). table x. mux control settings mel mer input setting 0x left channel analog buffer enabled 1x left channel analog buffer disabled x0 right channel analog buffer enabled x1 right channel analog buffer disabled mux select the mux select bits (mxl and mxr for left and right channels, respectively) are used to select the input from vinxp or vinxn when the input is configured as single-ended. when mxx is set to 0, the input is taken from vinxp. when mxx is set to 1, the input is taken from vinxn, (see table xi). table xi. mux select settings * mxl mxr input setting 0x left channel input from vinlp 1x left channel input from vinln x0 right channel input from vinrp x1 right channel input from vinrn * mux select settings are only valid when single-ended operation is enabled; sel and ser are set to 1.
ad1871 ?4 rev. 0 peak reading registers the peak reading registers are read-only registers that can be enabled to track-and-hold the peak adc reading from each channel. the peak reading feature is enabled by setting bit pre in control register i. the peak reading value is contained in the six lsbs of the 10-bit readback word. the result is binary coded where each lsb is equivalent to ? dbfs with all zeros cor- responding to full scale (0 dbfs) and all ones corresponding to ?3 dbfs (see table xvi). when bit pre is set, the peak reading per channel is stored in the appropriate peak register. once the register is read, the register value is set to zero and is updated by subsequent conversions. table xvi. peak reading result format code axp 5 4 3 2 1 0 level 000000 0 dbfs 000001 ? dbfs 000010 ? dbfs 11 1 110 ?2 dbfs 11 1 111 ?3 dbfs a peak reading register read cycle is detailed in figure 21. external control the ad1871 can be configured for external hardware control of a subset of the device functionality. this functionality includes master /slave mode select, mclk select, and serial data format select. external control is enabled by tying the xctrl pin high as shown in figure 22. 256 /512 m /s df0 df1 ad1871 xctrl v dd figure 22. external control configuration table xiv. peak reading register i (address 0011b, read-only) 15?2 11 10 9 87 6 5 432 10 0011 1 0 a0p5 a0p4 a0p3 a0p2 a0p1 a0p0 9? reserved (always set to zero) 5? a0p5?0p0 left channel peak reading (valid only when pre = 1) table xv. peak reading register ii (address 0100b, read-only) 15?2 11 10 9 87 6 5 432 10 0100 1 0 a1p5 a1p4 a1p3 a1p2 a1p1 a1p0 9? reserved (always set to zero) 5? a1p5?1p0 right channel peak reading (valid only when pre = 1) master /slave select the master /slave hardware select (pin 5, clatch/[ m /s]) is equivalent to setting the m /s bit of control register ii. if set low, the device is placed in master mode, whereby the lrclk and bclk signals are outputs from the ad1871. when m /s is set high, the device is in slave mode, whereby the lrck and bclk signals are inputs to the ad1871. mclk mode select the mclk mode hardware select (pin 2, cclk/[ 256 /512]) is a subset of the mclk mode selection that is determined by bits cm1?m0 of control register x. when the hardware pin is low, the device operates with an mclk that is 256 f s ; if the pin is set high, the device operates with an mclk that is 512 f s . serial data format select the serial data format hardware select (pins 3 and 4, df0/ cout and df1/cin) is equivalent to setting bits df1?f0 of control register ii. see table viii. in external control mode, all functions other than those selected by the hardware select pins ( master /slave mode select, mclk select, and serial data format select) are in their default (power-on) state. modulator mode when the device is in modulator mode (mme bit is set to 1), the d[0?] pins are enabled as data outputs, while the cout pin becomes modclk, a high speed sampling clock (nomi- nally at 128 f s ). the modclk enables successive data from the left and right channel modulators with left channel modula- tor data being valid in the low phase of modclk, while right channel modulator data is valid under the high phase of modclk (see modulator mode timing in figure 6). the modulator mode is designed to be used for applications such as direct stream digital (dsd) where modulator data is stored directly to the recording media without decimation and filtering to a lower sample rate. dsd is specified at a rate of 64 f s , whereas the ad1871 outputs at 128 f s , requiring an intermediate remodulator that downsamples to 64 f s and generates a single-bit output steam.
rev. 0 ad1871 ?5 interfacing analog interfacing the analog section of the ad1871 has been designed to offer flexibility as well as high performance. users may choose full differ ential input directly to the adc? - modulator via pins capxp and capxn. alternatively, when using the on-chip pga section, it is also possible to multiplex single-ended inputs on pins vinxp and vinxn or to use these pins for full differential input. whichever input topology is chosen (direct or via mux/pga section), the modulator input pins (capxp and capxn) require capacitors to act as dynamic charge storage for the switched capacitor input section. component selection for these capacitors is critical as the input audio signal appears on or across these capacitors. a high quality dielectric is recommended for these capacitors multilayer ceramic, npo or metal film, pps for surface-mounted versions, and polypropylene for through-hole versions. indeed, as a general recommendation, high quality dielec trics should be specified where capacitors are carrying the input audio signal. modulator direct input figure 23 shows the connection of a single-ended source via an external single-ended-to-differential converter to the modulator input of the ad1871. the external amplifier/buffer should have good slew rate characteristics to meet the dynamic characteristics of the modulator input that is a switched-capacitor load. the output of the external amplifier/buffer should be decoupled from the input capacitors via a 250 w resistor (metal film). in order to configure the ad1871 for differential input via the capxp and capxn pins, the mux/pga section must be disabled by setting the mel and mer bits in control register iii to 1. op275 1nf npo 100pf npo 100pf npo 120pf npo 5.76k 750k 237 capln caplp vref ad1871 10 f ferrite 100nf 237 100pf npo 5.76k 5.76k 10 f 5.76k op275 figure 23. direct connection to modulator pga input, single-ended figure 24 shows the connection of a single-ended source to the pga section of the ad1871. the pga section is configured for single-ended-to-differential conversion. the differential out puts are connected internally to the capxx pins via 250 w series resistors. in order to configure the ad1871 for single-ended input, the control registers must be configured as follows: left channel control register i = xx0xgggxxx, where ggg = the input gain (see table v). control register iii = 00xx1x0sxx, where s = the se channel selection. r ight channel control register i = xx0xxxxggg, where ggg = the input gain (see table v). control register iii = 00xxx1xx0s, where s = the se channel selection. 1nf npo 100pf npo 100pf npo capln caplp ad1871 vref 10 f 100nf vinlp vinln 10 f ferrite 600z 100pf npo figure 24. single-ended input via pga section pga input, differential figure 25 shows the connection of a differential source to the pga section of the ad1871. the pga section is configured as a differential buffer. the buffered differential outputs are con- nected internally to the capxx pins via a 250 w series resistors. in order to configure the ad1871 for differential input via the mux/pga, the control registers must be configured as follows: left channel control register i = xx0xgggxxx, where ggg = the input gain (see table v). control register iii = 00xx0x0xxx. right channel control register i = xx0xxxxggg, where ggg = the input gain (see table v). control register iii = 00xxx0xx0x. 1nf npo 100pf npo 100pf npo capln caplp ad1871 vref 10 f 100nf vinlp vinln 10 f 10 f 2 3 1 figure 25. differential input via pga section
ad1871 ?6 rev. 0 layout considerations in order to operate the ad1871 at its specified performance level, careful consideration must be given to the layout of the ad1871 and its ancillary circuits. since the analog inputs to the ad1871 are differential, the voltages in the analog modula tor are common- mode voltages. the excellent common-mode rejection of the part will remove common-mode noise on these inputs. the analog and digital supplies of the ad1871 are independent and sepa- rately pinned out to minimize coupling between the analog and digital sections of the device. the digital filters will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. the digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modulator. however, because the resolution of the ad1871? adc is high, and the noise levels from the ad1871 are so low, care must be taken with regard to grounding and layout. the printed circuit board that houses the ad1871 should be designed so the analog and digital sections are separated and confined to certain sections of the board. the ad1871 pin selection has been configured such that its analog and digital interfaces are connected on opposite ends of the package. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. figure 26 is a view of the ground plane separation (between analog and digital) in the area surrounding the ad1871, taken from the layout of the ad1871 evaluation board (eval-ad1871eb). figure 26. ground layout * in the above figure, the black area represents the solder side of the layout. the silkscreen in white is included for clarity. digital and analog ground planes should be joined in only one place. if this connection is close to the device, it is recom- mended to use a short (0 w resistor) or ferrite bead inductor as shown in figure 27. the pads for the ferrite are positioned on the solder side directly underneath the ad1871 device. avoid running digital lines under the device as they may couple noise onto the die. the analog ground plane should be allowed to run under the ad1871 to avoid noise coupling. if it is not possible to use a power supply plane, the power supply lines to the ad1871 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground planes while the signals are placed on the other side. figure 27. connecting analog and digital grounds good decoupling is important when using high speed devices. all analog and digital supplies should be decoupled to agnd and dgnd, respectively, with 0.1 m f ceramic capacitors in parallel with 10 m f tantalum capacitors. to achieve the best from these decoupling capacitors, they should be placed as close as possible to the device, ideally right up against it, as shown in figure 28. in systems where a common supply voltage is used to drive both the avdd and dvdd of the ad1871, it is recom- mended that the system? avdd supply be used. this supply should have the recommended analog supply decoupling between the avdd pins of the ad1871 and agnd and the recommended d igital supply decoupling capacitors between the dvdd pin and dgnd. figure 28. ad1871 power supply decoupling another important consideration is the selection of components such as capacitors, resistors, and operational amplifiers for the ancillary circuits. the capacitors that are used should in the analog audio signal chain should be of npo dielectric (if ceramic) or metal film. figure 28 shows the placement of the capxx pin capacitors relative to the capxx pins. the placement is intended to keep the tracking between the capacitor and the pin as short as possible while also ensuring that the track length from capxp pin to its capacitor equals that of the capxn to its capacitor.
rev. 0 ad1871 ?7 outline dimensions 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters 0.25 0.09 0.95 0.75 0.55 8 4 0 0.05 min 1.85 1.75 1.65 2.00 max 0.38 0.22 seating plane 0.65 bsc 0.10 coplanarity 28 15 14 1 10.50 10.20 9.90 pin 1 5.60 5.30 5.00 8.20 7.80 7.40 compliant to jedec standards mo-150ah
?8 c02644??/02(0) printed in u.s.a.

▲Up To Search▲

Price & Availability of AD1871YRS-REEL

	To Download AD1871YRS-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .